`timescale 1ns / 1ps

module AD_CLK
    #(
        parameter dclk_div = 10
    )(
        input clk_1GH,      // 外部输入
        input clk_en,
        output FCLK,
        output DCLK,
        output DCLK0,
        output L_P,
        output L_N
    );

    reg[15:0] cnt_d=16'd0, cnt_f=16'd0;
    reg FCLK_r = 1'b0;
    reg DCLK_r = 1'b0;
    reg DCLK0_r = 1'b0;
    reg[31:0] DCLK_dly_r = 32'b0;

    // reg[15:0] mock_data = 16'b1111_1100_1010_0011;
    reg[15:0] mock_data = 16'b1010_1010_1010_1010;

    assign FCLK = FCLK_r;
    assign DCLK0= DCLK0_r;
    
    assign DCLK = DCLK_dly_r[22];

    // generate DCLK0
    always@( posedge clk_1GH ) begin
        if( clk_en == 1'b0 ) begin
            cnt_d[15:0] <= 16'b0;
            DCLK0_r <= 1'b0;
        end
        else begin
            if( cnt_d < 16'd9 ) begin
                cnt_d <= cnt_d + 16'b1;
            end
            else begin
                DCLK0_r <= ~DCLK0_r;
                cnt_d <= 16'b0;
            end
        end
    end

    always@(posedge DCLK0) begin
        DCLK_r <= ~DCLK_r;
    end


    // always@( posedge clk_1GH ) begin
    //     if( clk_en == 1'b0 ) begin
    //         cnt_f[15:0] <= 16'b0;
    //         FCLK_r <= 1'b0;
    //     end
    //     else begin
    //         if( cnt_f < 16'd140 ) begin
    //             cnt_f <= cnt_f + 16'b1;
    //         end
    //         else begin
    //             FCLK_r <= ~FCLK_r;
    //             cnt_f <= 16'b0;
    //         end
    //     end
    // end

    always@( posedge DCLK0_r ) begin
        if( clk_en == 1'b0 ) begin
            cnt_f[15:0] <= 16'b0;
            FCLK_r <= 1'b0;
        end
        else begin
            if( cnt_f < 16'd6 ) begin
                cnt_f <= cnt_f + 16'b1;
            end
            else begin
                FCLK_r <= ~FCLK_r;
                cnt_f <= 16'b0;
            end
        end
    end

    always@( posedge clk_1GH ) begin
        // DCLK_dly_r[0] <= DCLK_dly_r[1];
        // DCLK_dly_r[1] <= DCLK_dly_r[2];
        // DCLK_dly_r[2] <= DCLK_dly_r[3];
        // DCLK_dly_r[3] <= DCLK_dly_r[4];
        // DCLK_dly_r[4] <= DCLK_dly_r[5];
        // DCLK_dly_r[5] <= DCLK_dly_r[6];
        // DCLK_dly_r[6] <= DCLK_dly_r[7];
        // DCLK_dly_r[7] <= DCLK_dly_r[8];
        // DCLK_dly_r[8] <= DCLK_dly_r[9];
        // DCLK_dly_r[9] <= DCLK_dly_r[10];
        // DCLK_dly_r[10] <= DCLK_dly_r[11];
        // DCLK_dly_r[11] <= DCLK_dly_r[12];
        // DCLK_dly_r[12] <= DCLK_dly_r[13];
        // DCLK_dly_r[13] <= DCLK_dly_r[14];
        // DCLK_dly_r[14] <= DCLK_dly_r[15];
        // DCLK_dly_r[15] <= DCLK_dly_r[16];
        // DCLK_dly_r[16] <= DCLK_dly_r[17];
        // DCLK_dly_r[17] <= DCLK_dly_r[18];
        // DCLK_dly_r[18] <= DCLK_dly_r[19];
        // DCLK_dly_r[19] <= DCLK_dly_r[20];
        // DCLK_dly_r[20] <= DCLK_dly_r[21];
        // DCLK_dly_r[21] <= DCLK_dly_r[22];
        // DCLK_dly_r[22] <= DCLK_dly_r[23];
        // DCLK_dly_r[23] <= DCLK_dly_r[24];
        // DCLK_dly_r[24] <= DCLK_dly_r[25];
        // DCLK_dly_r[25] <= DCLK_dly_r[26];
        // DCLK_dly_r[26] <= DCLK_dly_r[27];
        // DCLK_dly_r[27] <= DCLK_dly_r[28];
        // DCLK_dly_r[28] <= DCLK_dly_r[29];
        // DCLK_dly_r[29] <= DCLK_dly_r[30];
        // DCLK_dly_r[30] <= DCLK_dly_r[31];
        DCLK_dly_r[30:0] <= DCLK_dly_r[31:1];
        DCLK_dly_r[31] <= DCLK_r;
    end


    always@( posedge DCLK0_r) begin
        mock_data <= {mock_data[14:0], mock_data[15]};
    end

    assign L_P = mock_data[0];
    assign L_N = ~mock_data[0];


endmodule
